This invention relates to a digital conferencing system and more particularly, to a time slot interchanger for buffering information from one time slot bus to a second time slot bus.
In a time division distributed conferencing system of the type disclosed in copending concurrently filed patent application of Baxter, Berkowitz and Buzzard, Ser. No. 256,937, which application is hereby incorporated by reference herein, conferences are formed between terminals remotely located from a central processor. In such a situation it is necessary to remove signal samples from a system bus having a large number of time slots and to assemble several samples together for distribution to the terminals grouped at the remote location. The assembled samples must be compiled within a given time frame and provided to the stations over a station bus having a different number of time slots than does the system bus. A further constraint on the system is that each assembled conference must be capable of having each sample individually modified by a variable preset transmission gain value. Since the system may have numerous such groups of terminals, it is necessary to insure that the processing which must be done at each group is minimized.
Thus, it is desired to construct a time multiplexed system with time slot interchange capability and with the ability to conference together a group of time slots for a given communication connection. A typical prior time slot interchanger is constructed using a time slot assignment (TSA) memory and two sample buffer memories. The TSA memory contains, for each time slot, an instruction which points to a location within the sample buffer. The system processor loads the instructions into the TSA memory for each communication connection. A time slot clock operates to sequence through the TSA memory and for a given time slot address in the TSA memory a sample buffer memory address is provided. The data sample associated with the given time slot is loaded into the sample buffer at the location therein identified by the address obtained from the TSA memory. This system is shown in copending patent application of R. P. Abbott, et al., Ser. No. 73,849, now U.S. Pat. No. 4,298,977, issued Nov. 3, 1981. The Abbott disclosure, while advantageous from the time slot interchange standpoint, requires the time slot address memory to have as many memory locations as there are input bus time slots. In addition, when establishing the sample buffer address in the time slot address memory, only one sample buffer address can be used for each time slot address memory. Thus, the Abbott system is not designed to form conferences between time slots, since for conference capability, the same time slot sample must be stored in more than one buffer location.